AMIR MABHOUT

Dr.-Ing.  ·  Research Engineer

Amir Mabhout

AI agents, RL environments, and evaluations for chip design and EDA workflows.

Co-founder of Simra AI. Before that: analog and mixed-signal designer with four tapeouts, from 22 nm FDSOI Ethernet PHY circuits to 180 nm energy harvesting.

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Autonomous chip design house — a team of agents designing a chip toward tapeout, streaming 24/7

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Career floorplan An abstract chip layout whose blocks are Amir's areas of work: agents and EDA orchestration, RL environments, evaluations and benchmarks, plus the analog blocks he taped out — Ethernet PHY, TX-DAC, impedance calibration, charge pump — and Simra AI and the live autonomous design house. Analog blocks link to the corresponding IEEE papers; the rest link to the matching page sections. AM-2026  REV 2.0 0,0 Agents & EDA orchestration — see Selected work AGENTS EDA ORCHESTRATION 0x04 RL environments — see Selected work RL ENVIRONMENTS 0x04 Evaluations & benchmarks — see Selected work EVALS & BENCHMARKS 0x04 Ethernet PHY DAC driver in 22nm CMOS — IEEE SSC-L 2021, ref [1] ETH PHY 22nm FDSOI [1] 3.2 GS/s TX-DAC compensation — IEEE MWSCAS 2017, ref [4] TX-DAC 3.2 GS/s [4] Impedance calibration in 22nm FDSOI — IEEE MWSCAS 2019, ref [2] IMPEDANCE CAL [2] Fully integrated charge pump — IEEE MWSCAS 2017, ref [3] CHARGE PUMP [3] SIMRA AI ↗ LIVE 24/7
fig. 0 — career floorplan  ·  blocks link to papers & sections
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Profile

Dr.-Ing. Amir Mabhout
fig. 1 — Dr.-Ing. Amir Mabhout

I spent years doing analog and mixed-signal chip work the hard way: schematics, layout, simulation, post-layout debug, tapeout pressure, and the small judgement calls that never fit cleanly into a textbook. Simra is the tool I wanted during those loops.

My work spans EDA orchestration and the creation of RL tasks, evaluations, and benchmarks for engineering agents, with an emphasis on electronics and chip-design workflows. Simra sits beside existing toolchains, runs repetitive work, captures evidence, and brings engineers back in when judgement matters.

Before Simra I explored data ownership, crypto, agents, and consumer products. A lot of that was useful training, but the real pull was back to chip design: a difficult, high-trust field where better software can save expert engineers from endless manual glue work.

  • 4 chip tapeouts — 22 nm FDSOI to 180 nm
  • 8 IEEE publications, 5 first-author
  • Dr.-Ing., mixed-signal circuit design, TU Berlin
  • Co-founder, Simra AI
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Selected work

Simra AI 

EDA orchestration for analog and mixed-signal teams: existing tools, private environments, repeatable evidence, and engineer signoff. Simulation and debug loops, PDK-aware migration checks, verification evidence, workflow memory.

Revision history

  1. rev 0.12011–2015

    M.Sc. Microsystems Engineering

    IMTEK, University of Freiburg. Multidisciplinary systems engineering across mechanical, fluidic, and electrical domains, with a focus on circuit and system design.

  2. rev 1.02016–2020

    Dr.-Ing., mixed-signal circuit design — first silicon

    PhD at TU Berlin with multiple tapeouts, including 22 nm FDSOI high-speed Ethernet PHY circuits and 180 nm energy-harvesting work. Publications below, refs [1]–[8].

  3. rev 1.12021–2023

    Teaching, software, and product reps

    Taught electromagnetism, then built Datalatte and survey/data experiments. The useful lesson: start from a painful workflow, not from an ideology about technology.

  4. rev 1.22023–2024

    Fast experiments

    Hackathons as quick product reps around privacy, data, social graphs, and agents: ETHMunich (2nd place, AI track), ETHRome (5 bounties), ETHGlobal Bangkok (Circles 1st bounty), and the SAFE Agentathon (agent matchmaking).

  5. rev 2.02024–now

    Simra AI — current revision

    Co-founder. Agents, RL tasks, evaluations, and benchmarks for chip design and EDA workflows, plus the live autonomous design house.

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Publications

First-author

  1. [1] A 9-bit, 45 mW, 0.05 mm² source-series-terminated DAC driver with echo canceller in 22-nm CMOS for in-vehicle communicationIEEE Solid-State Circuits Letters, 2021
  2. [2] Impedance calibration technique canceling process and temperature variation in source terminated DAC drivers in 22nm FDSOIIEEE MWSCAS, 2019
  3. [3] A fully integrated charge pump using parasitics to increase usable capacitance by 25% and efficiency by up to 18%IEEE MWSCAS, 2017
  4. [4] Analysis and compensation technique canceling non-linear switch and package impedance effects of a 3.2GS/s TX-DACIEEE MWSCAS, 2017
  5. [5] A digital calibration technique canceling non-linear switch and package impedance effects of a 1.6GS/s TX-DAC in 28 nm CMOSIEEE ISCAS, 2017

Co-authored

  1. [6] Advanced mixed-signal concepts exploiting the strong body-bias effect in CMOS 22FDXIEEE TCAS I, 2021
  2. [7] Body-bias techniques in CMOS 22FDX for mixed-signal circuits and systemsIEEE ICECS, 2019
  3. [8] Analysis of package impedance effects on the linearity of source-series-terminated DACsIEEE MWSCAS, 2018
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Contact

Reach out if you work on analog or mixed-signal design, EDA workflows, RL environments, engineering evaluations, silicon IP reuse, or useful AI agents for hard engineering domains.

[email protected]

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