AMIR MABHOUT

Dr.-Ing.  ·  Research Engineer

Amir Mabhout

AI agents, RL environments, and evaluations for chip design and EDA workflows.

Co-founder of Simra AI. Before that: four tapeouts as a chip designer, from X-FAB 130 nm energy harvesting to 22 nm FDSOI Ethernet PHY circuits.

Expertise Analog and mixed-signal — the corner of chip design automation left behind. Digital is synthesised and largely automated; analog is still hand-drawn and simulation-bound, roughly 40× less automated. That gap is the work.

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Autonomous chip design house — a team of agents designing a chip toward tapeout, streaming 24/7

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Career floorplan An abstract chip layout in two labelled regions. The upper region is current work — agents and EDA orchestration, evaluations and benchmarks, RL environments. The lower region is the analog and mixed-signal expertise: four taped-out blocks — Ethernet PHY in 22 nm FDSOI, a 3.2 GS/s TX-DAC, impedance calibration, and an X-FAB 130 nm energy-harvesting charge pump. Below both sit Simra AI and the live autonomous design house. Analog blocks link to the corresponding IEEE papers; the rest link to the matching page sections. AM-2026  REV 2.0 0,0 CURRENT · AI FOR CHIP DESIGN Agents & EDA orchestration — see Selected work AGENTS EDA ORCHESTRATION 0x04 Evaluations & benchmarks — see Selected work EVALS & BENCHMARKS 0x04 RL environments — see Selected work RL ENVIRONMENTS TASKS & REWARDS FOR ENGINEERING AGENTS 0x04 EXPERTISE · ANALOG & MIXED-SIGNAL · 4 TAPEOUTS Ethernet PHY DAC driver in 22nm CMOS — IEEE SSC-L 2021, ref [1] ETH PHY 22nm FDSOI [1] 3.2 GS/s TX-DAC compensation — IEEE MWSCAS 2017, ref [4] TX-DAC 3.2 GS/s [4] Impedance calibration in 22nm FDSOI — IEEE MWSCAS 2019, ref [2] IMPEDANCE CAL [2] Fully integrated charge pump for energy harvesting, X-FAB 130nm — first silicon, IEEE MWSCAS 2017, ref [3] CHARGE PUMP X-FAB 130nm [3] SIMRA AI ↗ LIVE 24/7
fig. 0 — career floorplan  ·  blocks link to papers & sections
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Profile

Dr.-Ing. Amir Mabhout
fig. 1 — Dr.-Ing. Amir Mabhout

I spent years doing chip design the hard way: schematics, layout, simulation, post-layout debug, tapeout pressure, and the small judgement calls that never fit cleanly into a textbook. Simra is the tool I wanted during those loops.

Within chip design, my expertise is analog and mixed-signal — and that is deliberate. Digital logic has three decades of synthesis, place-and-route, and formal tooling behind it; a designer there writes intent and lets the flow build the circuit. Analog has almost none of that. Devices are still sized by hand, layout drawn by hand, and correctness established one long simulation at a time. The result is a design-effort gap of roughly 40× against digital — and it is the part of the industry where good agents have the most left to give.

So my work spans EDA orchestration and the creation of RL tasks, evaluations, and benchmarks for engineering agents, aimed at exactly those loops. Simra sits beside existing toolchains, runs repetitive work, captures evidence, and brings engineers back in when judgement matters.

Before Simra I explored data ownership, crypto, agents, and consumer products. A lot of that was useful training, but the real pull was back to chip design: a difficult, high-trust field where better software can save expert engineers from endless manual glue work.

  • Analog & mixed-signal expertise — 4 tapeouts, X-FAB 130 nm to 22 nm FDSOI
  • 8 IEEE publications, 5 first-author
  • Dr.-Ing., mixed-signal circuit design, TU Berlin
  • Co-founder, Simra AI
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Selected work

Simra AI 

EDA orchestration for analog and mixed-signal teams: existing tools, private environments, repeatable evidence, and engineer signoff. Simulation and debug loops, PDK-aware migration checks, verification evidence, workflow memory.

Revision history

  1. rev 0.12011–2015

    M.Sc. Microsystems Engineering — first silicon

    IMTEK, University of Freiburg. Multidisciplinary systems engineering across mechanical, fluidic, and electrical domains, with a focus on circuit and system design. First tapeout here: a fully integrated charge pump for energy harvesting in X-FAB 130 nm, ref [3].

  2. rev 1.02016–2020

    Dr.-Ing., mixed-signal circuit design

    PhD at TU Berlin with multiple tapeouts, including 22 nm FDSOI high-speed Ethernet PHY circuits and source-terminated DAC driver work. Publications below, refs [1]–[8].

  3. rev 1.12021–2023

    Teaching, software, and product reps

    Taught electromagnetism, then built Datalatte and survey/data experiments. The useful lesson: start from a painful workflow, not from an ideology about technology.

  4. rev 1.22023–2024

    Fast experiments

    Hackathons as quick product reps around privacy, data, social graphs, and agents: ETHMunich (2nd place, AI track), ETHRome (5 bounties), ETHGlobal Bangkok (Circles 1st bounty), and the SAFE Agentathon (agent matchmaking).

  5. rev 2.02024–now

    Simra AI — current revision

    Co-founder. Agents, RL tasks, evaluations, and benchmarks for chip design and EDA workflows, plus the live autonomous design house.

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Publications

First-author

  1. [1] A 9-bit, 45 mW, 0.05 mm² source-series-terminated DAC driver with echo canceller in 22-nm CMOS for in-vehicle communicationIEEE Solid-State Circuits Letters, 2021
  2. [2] Impedance calibration technique canceling process and temperature variation in source terminated DAC drivers in 22nm FDSOIIEEE MWSCAS, 2019
  3. [3] A fully integrated charge pump using parasitics to increase usable capacitance by 25% and efficiency by up to 18%IEEE MWSCAS, 2017
  4. [4] Analysis and compensation technique canceling non-linear switch and package impedance effects of a 3.2GS/s TX-DACIEEE MWSCAS, 2017
  5. [5] A digital calibration technique canceling non-linear switch and package impedance effects of a 1.6GS/s TX-DAC in 28 nm CMOSIEEE ISCAS, 2017

Co-authored

  1. [6] Advanced mixed-signal concepts exploiting the strong body-bias effect in CMOS 22FDXIEEE TCAS I, 2021
  2. [7] Body-bias techniques in CMOS 22FDX for mixed-signal circuits and systemsIEEE ICECS, 2019
  3. [8] Analysis of package impedance effects on the linearity of source-series-terminated DACsIEEE MWSCAS, 2018
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Contact

Reach out if you work on chip design — especially analog and mixed-signal — EDA workflows, RL environments, engineering evaluations, silicon IP reuse, or useful AI agents for hard engineering domains.

[email protected]

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